Authors:

Ohik Kwon

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About Paper:

Due to the increasing demand for high-performance chips with greater functionality, transistors have continued to scale according to Moore's Law. However, as we approach the limitations of transistor scaling, 3D integrations have emerged as a promising solution to enhance the power and performance of chips. One crucial technology enabling vertical chip stacking is Through Silicon Vias (TSV). By utilizing Buried Power Rails (BPR) and Nano TSV (nTSV), which separate signal and power wires and position the power signals at the back side of wafers, improved Power Performance Area (PPA) is achieved. This technique holds great promise for further enhancing chip performance. Nevertheless, the complex fabrication process and the electrical performance of the BPR+nTSV structure on a device chip are not yet fully understood. Previous research has focused on analyzing the impact of simplified BPR+nTSV electrical simulations on IR drop and the device's thermal stress through thermo-mechanical simulations. However, there is a lack of comprehensive research examining the contact resistance and resistance of different materials (such as barrier or liner layers) in the nano-scale regime. In this study, we employ ab-initio simulations to obtain the electrical properties of materials at the nano-scale and investigate their influence on the BPR+nTSV structure. Our aim is to present a thorough analysis of the electrical performance of the BPR+nTSV structure, considering various material combinations and geometries. By doing so, we seek to deepen the understanding of the electrical properties of the BPR+nTSV structure necessary for the intensive scaling of both devices and BPR+nTSV structures.

Source:

Purdue University / 2023

Topics:

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Co-authors:

Ohik Kwon