Authors:

Yiyang Shui

Date Created:

Not specified

Course Title:

Professor:

Not specified

About Paper:

AFTx07 is a RISC-V based microcontroller under design by the SoCET team, to be taped out in October 2023. In particular, the AFTx07 project concerns implementation of digital modules using hardware description language and computer architecture design principles, all of which are critical to the successful fabrication of the design. To properly design and test AFTx07 prior to tape-out, the team has been using SystemVerilog to create custom digital modules that are simulated using tools such as Verilator and Xcelium. After passing simulation tests, the design is synthesized to gate-level netlist using electronic design automation (EDA) tools such as Cadence Genus. FPGA synthesis is done using Quartus Prime software, and then tested on FPGA hardware. FPGA hardware tester module has also been developed to validate individual AFTx07 components on bus level. For AFTx07, beyond integration of peripheral modules, the team has established optimization and RTL goals to improve the functionality and performance of the SoC. Major achievement includes adding L1 caches to increase performance with respect to instruction and data fetches, and a buffered memory controller to interface the CPU with memory. The final product, AFTx07, will be able to provide the Purdue engineering community with the unique experience of testing and using a custom SoC. After tape-out, we plan to provide AFTx07 chips for use by other Purdue organizations that make use of microcontrollers, such as Purdue Electric Racing and Purdue IEEE teams.

Source:

Purdue University / 2023

Topics:

No topics listed

Co-authors:

Yiyang Shui