Authors:

Yunhao Lan

Date Created:

Not specified

Course Title:

Professor:

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About Paper:

This project aimed to integrate the digital input/output multiplexer (I/O MUX) onto the AFTx07, a system-on- chip (SoC) design by Purdue SoCET Team. To be specific, this project did the integration of I/O MUX on the top-level chip, I/O MUX's connection with the advanced peripheral bus (APB), and the interconnection between IO MUX and the three integrated APB peripherals in the current branch of AFTx07: general-purpose input/output (GPIO), pulse width modulation (PWM), and serial peripheral interface (SPI). I/O MUX, acting as a digital multiplexer, allows for configuring the pins to be used for specific functions. It achieves this by having a function select register, direction signals, and data signals. In AFTx07, each pin is multiplexed by GPIO corresponding with the pin number and a signal needed by another peripheral. In this project, C-code tests were written that exercise the functionality of the I/O MUX. Thus, simulation was conducted in a way of configuring both I/O MUX and a peripheral to fulfill the peripheral's functionality and verified it through the outputs of the I/O MUX (both to input/output pad (I/O PAD) and to peripherals). Finally, the simulation of the I/O MUX passed for GPIO, PWM, and SPI, showing that I/O MUX's integration with these three APB peripherals on the top-level chip is well functioning.

Source:

Purdue University / 2023

Topics:

No topics listed

Co-authors:

Yunhao Lan