Authors:

William Rowan Cunningham

Date Created:

Not specified

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About Paper:

While scalar processors operate on a single element, vector processors operate on multiple elements simultaneously. This form of data-level parallelism in a processor is called Single Instruction Multiple Data (SIMD). Vector processors offer increased data throughput compared to scalar processors, leading to a significant performance boost in data-intensive applications such as image processing or artificial intelligence. RISC-V's "V" vector extension outlines specifications and enables support for SIMD operations. Vectors can be loaded from and stored in main memory; however, memory operations bottleneck the current design's performance. While scalar load and store instructions only make one memory access per instruction, vector load and store instructions make memory accesses for each vector element. This research aims to improve vector unit performance by reducing memory accesses. The read-and-write data lanes between the data cache and load store controller were widened to return the entire cache block. Vector element addresses that match tags and go to the same cache block access memory at the same time. Grouping memory accesses together does not always happen, as coalescing is executed when convenient. After running a suite of custom scalar and vector benchmarks, the total number of cycles for each benchmark will be collected to evaluate performance. Then, the design will be synthesized to determine the maximum clock frequency, power, and area. Future work can focus on throughput improvements between processor interconnects. Keywords: Computer Engineering; Vector Processors

Source:

Purdue University / 2024

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No topics listed

Co-authors:

William Rowan Cunningham