Authors:

Indrayudh Chowdhury

Date Created:

Not specified

Course Title:

Professor:

Not specified

About Paper:

This project focuses on verifying a Platform-Level Interrupt Controller (PLIC) using Universal Verification Methodology (UVM). Initial efforts involved developing a test plan and architecture. Following this, directed sequences were created to test the PLIC UVM test bench. Once the test bench's validity was confirmed, the focus shifted to the PLIC design, utilizing randomized test sequences to ensure comprehensive functional coverage. This verification approach highlights both the robustness of the PLIC design and the test bench's capability to assess its performance effectively. Robust verification is crucial to ensure the reliability and correctness of critical hardware components in complex systems. Keywords: Interrupt Controller; Universal Verification Methodology; Functional Coverage; Randomized Sequences; Verification

Source:

Purdue University / 2024

Topics:

No topics listed

Co-authors:

Indrayudh Chowdhury