Authors:

Abhijay Achukola

Date Created:

Not specified

Course Title:

Professor:

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About Paper:

In microcontroller architecture, the ability to store more programs or more instructions allows for more functionality and more complex programs to better operate on microcontrollers. We implemented the C, or compressed instruction, extension in the RISC-V core, including some instructions that do not have 32-bit equivalents, such as push and pop instructions as well as table jump instructions which fall under the Zcmp and Zcmt subsets of the C extension. The new instructions added provide valuable utility to developers as the push and pop instructions allow saving register values before and after a function call and table jump instructions allow for things such as the creation of a vectored interrupt table for better interrupt handling in the microcontroller. While other compressed instructions were simply implemented by converting them to their 32- bit equivalents, these instructions had to be tackled differently as multiple 32-bit instructions were needed to implement one 16-bit instruction. This was done by using a ROM to store a database of 32-bit instructions that each of these new 16-bit instructions decode into and using a state machine to send the correct 32-bit instructions while stalling the fetching of the next instruction until the 16-bit instruction has been fully processed. To implement and verify that that the C extension works with the existing core, SystemVerilog was used as the HDL and Verilator was used for simulation. Custom RISC-V assembly test cases were also written to test and verify the new compressed instructions implemented operate as intended. Keywords: RISC-V; Instruction Sets; CPU Architecture

Source:

Purdue University / 2024

Topics:

No topics listed

Co-authors:

Abhijay Achukola