Authors:

Michael Jeffery Dick

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About Paper:

AHB is a high performance bus architecture used to connect and manage the functional blocks of a system-on- chip design. SoCET's AFTx07 SoC design utilizes the AHB bus to connect the CPU to different blocks of the design as well as connecting to the slower APB bus that connects to the design's peripherals. The task of our research this summer has been to make updates to the implementation of the AHB bus to allow for different data widths and address widths to be used. This involves implementing parameterization into AHB components to select address and data bus widths. This also includes updating the implementation of the HSIZE signal to match the AMBA 5 spec. Then once these changes are implemented a bridge is required to connect buses that are different sizes as well as an update to the bridge that connects the faster AHB bus to the slower APB bus. This bridge along with the updates to the AHB bus implementation will allow the CPU to request larger data widths than other blocks can provide in a single transaction. Keywords: System on Chip; Bus Protocols; AMBA

Source:

Purdue University / 2024

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Co-authors:

Michael Jeffery Dick