Authors:

Katelyn Krishan Shah

Date Created:

Not specified

Course Title:

Professor:

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About Paper:

SoCET's research project aims to extend, optimize, and prepare a general-purpose system-on-chip (SoC) for fabrication and testing. The primary objective of the upcoming AFTx08 tapeout is to improve upon the performance and integration metrics of the AFTx07 chip, through improved multi-core CPU functionality, new peripheral extensions, and architectural refinements. As part of the tapeout configuration and testing team, our focus is on integrating key modules, such as the branch predictor developed in Spring 2025, and connecting peripherals on the chip and FPGA levels. Our team is exploring architectural tradeoffs from adjusting cache sizes and interconnect configurations for performance. We are also evaluating simulation data to determine optimal configuration parameters and are preparing benchmark datasets for CPU and memory latency characterization. Currently, the design is in the pre- silicon integration phase, and subsystems are being validated. Tapeout for AFTx08 is scheduled for Fall 2025, where the chip will make progress to fabrication and post-silicon testing. Keywords: System-on-Chip; Tapeout; Performance Optimization; RISC-V; SoCET

Source:

Purdue University / 2025

Topics:

No topics listed

Co-authors:

Katelyn Krishan Shah