Authors:

Blake Alex

Date Created:

Not specified

Course Title:

Professor:

Not specified

About Paper:

This presentation will detail steps pertinent to the System-on-Chip design flow process. The flow process begins with hardware description code (SystemVerilog), then proceeds by synthesizing a digital circuit schematic from this code. After the digital circuit, a chip layout will be performed, where the physical placement of hardware is described for the entirety of the chip. Finally, the functionality of the chip is tested during the verification step, after which the chip is ready for manufacturing. Each step will be described for a general flow, discussing the impact of these steps on the flow process as a whole. Optimizations and design considerations will be included at each step. EDA tools (Cadence) will be discussed to show their usefulness in synthesizing and simulating complex chip designs much quicker than humans can manually. Keywords: [no keywords provided]

Source:

Purdue University / 2025

Topics:

No topics listed

Co-authors:

Blake Alex